A computer processor uses a so-called Instruction Set Architecture to talk with the world outside of its own circuitry. This ISA consists of a number of instructions, which essentially define the functionality of that processor, which explains why so many ISAs still exist today. It’s hard to find that one ISA that works for as many distinct use cases as possible, after all.
A fairly new ISA is RISC-V, the first version of which was created back in 2010 at the University of California, Berkeley. Intended to be a fully open ISA, targeting both students (as a learning tool) and industrial users, it is claimed to incorporate a number of design choices that should make it more attractive for a number of applications.
In this article I’ll take a look behind the marketing to take stock of how exactly RISC-V differs from other open ISAs, including Power, SPARC and MIPS.
Welcome to the World of RISC
A Reduced Instruction Set Computer (RISC) is a type of ISA which focuses on creating an instruction set that requires only a limited number of processor cycles to execute a single instruction. Ideally, an instruction would take exactly one cycle. This is in contrast to a Complex Instruction Set Computer (CISC), which focuses on reducing the number of instructions needed for an application, which decreases code storage requirements.
These days CISC is essentially no more, with the Motorola m68k ISA put out to pasture, and any CPU based on Intel’s x86 CISC ISA and successors (like AMD’s 64-bit extensions) being internally a RISC p ..
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