While there has been no shortage of FPGA-based recreations of classic processors, we always enjoy seeing a new approach. Last month [Some Assembly Required] took on the challenge to recreate a classic computer from the ground up and started with a 6502 implementation in Verilog. You can see in the second video below that he’s made good progress and there are apparently more videos to come.
The ROL instruction is the subject of the second video. We liked the approach of looking at what the instruction does and how many cycles it takes on different variants It is always good to make sure you know exactly what you are trying to accomplish before you get started.
We also like that the tutorial used some of the more interesting features of Vivado like automatic verification. Even if you are experienced with Verilog, there are some good tips here.
In the end, he’s still a good way from his final goal, but it looks like he’ll get there and we’ll be interested in seeing the rest of the video series as it completes.
The 6502 is a popular retrocomputing target. One of the tools this project uses is the Visual 6502 which we’ve covered before. That same simulation has ARM1 and 6800 targets, too.
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