Some people state that ESP8266 is tolerant of 5 V logic levels on its GPIOs, while others vehemently disagree, pointing at the datasheet-stated 3.6 V maximum. Datasheets aren’t source code for compiling the chip, however, and aren’t universally correct and complete either. [Avian] decided to dig deeper into the claims, conduct an experiment with an actual ESP8266 chip, then share the results for all of us.
For the experiment, he used a curve tracer – a device capable of producing a wide range of voltages and measuring the current being consumed, then plotting the voltage-to-current relationship. This helps characterize all sorts of variables, from diode breakdown voltages to transistor characteristics. The curve tracer he uses is a capable and professional-looking DIY build of his, and arguably, deserves a separate write-up!
The reasoning behind [Avian]’s experiment is simple – if the pin, set to an input, starts consuming a higher amount of current at a certain voltage threshold, then there’s gotta be some chip-internal structure, intended or unintended, that would be damaged at this voltage. Curve tracer in hand, he set up an ESP-01 module to set a GPIO to input, and started increasing the voltage.
The tests have shown that, while there’s a reverse biased ESD diode from GPIO pins to ground, there don’t seem to be diodes from the GPIO pin to the VCC rail – and those are the primary concern for 5 V tolerance. There does seem to be something functionally akin to a 6 V Zener diode internally, which should clamp the voltage before it gets too ..
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