Semiconductor Engineering sat down to discuss security risks across multiple market segments with Helena Handschuh, security technologies fellow at Rambus; Mike Borza, principal security technologist for the Solutions Group at Synopsys; Steve Carlson, director of aerospace and defense solutions at Cadence; Alric Althoff, senior hardware security engineer at Tortuga Logic; and Joe Kiniry, principal scientist at Galois, an R&D center for national security. What follows are excerpts of that discussion, which was held live at the Virtual Hardware Security Summit. To view part one of this discussion, click here. Part two is here.
SE: As over-the air-updates and security patches are added in for a lot of different devices, does that impact performance and power?
Borza: Yes, and we see that happening with a lot of security algorithms. As we’ve discovered more and more ways in which some attack can be first accomplished, and then defended against, we’ve seen how badly some of the x86 computers have slowed down to address a lot of the microarchitecture attacks. There is a cost, and it comes in terms of performance, power consumption, and sometimes area or memory footprint.
Carlson: There is a tradeoff you can make with the cost per area of performance penalty. There are people who have security co-processors that are watching what’s going on, and they’ll interrupt when something happens. Those are always on and running, so you get a power penalty, as well. But you can lessen the performance impact. It’s not ..
Support the originator by clicking the read the rest link below.
