A recent trend has been to convert high-level constructs into FPGA code like Verilog or VHDL. Slice goes the other way: it converts very hardware-specific concepts to Verilog and aims to be a more expressive and easier to use language.
Why Slice? The project’s web page enumerates its design goals:
A clean, simple syntax that clearly exposes the flow of operations and where clock cycles are spent.
Precise rules regarding flow control (loops, calls) and their clock cycle consumption.
Familiar hardware constructs such as always blocks, instantiation, expression tracking (wires).
An optional flow-control oriented design style (automatic FSM generation), that naturally integrates within a design: while, break, subroutines.
The possibility to easily describe pipelines.
Automatically takes care of creating flip-flops for variables, with automatic pruning (e.g. const or bindings).
Generic interfaces and grouped IOs for easy reuse and modular designs.
Generic circuits that can be instantiated and reused easily.
Explicit clock domains and reset signals.
Familiar syntax with both C and Verilog inspired elements.
Inter-operates with Verilog, allowing to import and reuse existing modules.
Powerful LUA-based pre-processor.
There are several examples of the different styles of coding Slice supports, ranging from the obligatory blinking LED example to a RISC-V CPU and a video processing application. Here’s part of the blinking example, just to give you a taste of what it looks like:
algorithm main(output uint5 leds)
{
intensity less_intense;
uint26 cnt = 0;
leds := cnt[21,5] & {5{less_intense.pwm_bit}};
cnt := cnt + 1;
}
algorithm intensity(output uint1 pwm_bit)
{
uint16 ups_and_downs = 16b1110000000000000;
pwm_bit := ups_and_downs[0,1];
ups_and_downs := {ups_and_downs[0,1],ups_and_downs[1,15]};
}
Of course, the real benefit over straight Verilog is only apparent with some ..
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