I’ve had a fairly varied early part of my career in the semiconductors business: a series of events caused me to jump disciplines a little bit, and after one such event, I landed in the test engineering department at Philips Semiconductors. I was tasked with a variety of oddball projects, supporting engineering work, fixing broken ATE equipment, and given a absolute ton of training: Good times! Here’s a story that comes straight off the oddball pile.
We needed to assemble a crack team of experts and high-tail it to deepest darkest Wales, and sort out an urgent production problem. The brief was that the wafer probe yield was disastrous and the correlation wafer was not giving the correct results. Getting to the punch line is going to require some IC fabrication background, but if you like stories about silicon, or red-bearded test engineers, it’s worth it.
Integrated Circuit Design and Testability
The DFT process turning ordinary sequential logic into scan testable logic. Note the additional SI (Shift In) and SE (Scan Enable) lines and the scan chain hookup
The naïve IC design is one that forgoes testability in pursuit of die area, development time and some misplaced notion of simplicity. I cannot say how many times I’ve come across stories from the past where a new startup proudly makes silicon, but has almost no testability features and they get really hammered when trying to ramp up production.
The chip may be ‘right by design’ in that it is targeted correctly to the fabrication process, and on the bench, the product validation process may show it is within specification and appropriate for the custom ..
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